Non-volatile memory devices, such as electrical erasable programmable read-only memories (EEPROM) or flash EEPROMs usually comprise a relatively large amount of memory cells. The memory cells are, for example, modified MOSFET transistors with an additional floating gate or a nitride layer, which is used to store an electrical charge representing a programming state of the memory cell.
Such memory cells are usually arranged in an array structure, with the rows of the array being selected by an associated wordline and the columns of the array being selected by an associated bitline.
During manufacturing of such large semiconductor circuits, individual memory cells or entire rows or columns of the array can turn out to be defective. Consequently, in a wafer sort process, in which the memory devices are tested and defective cells are identified, these cells are marked as unusable.
In order to maintain the overall memory capacity of the memory device, most memory devices include a number of redundant columns of memory cells, which are configured to replace memory cells identified as being defective during the wafer sort process.
U.S. Pat. No. 5,968,183, which is incorporated herein by reference, describes a memory device with a column redundancy unit in a peripheral circuit area. In order to transfer data required by the column redundancy unit between the column redundancy unit and the memory area, a common data bus is used in a time-shared transfer approach.
According to the prior art, column redundancy data required to decide whether a particular memory cell of the array is being replaced by a cell in one of the redundant columns must be loaded over a data bus connecting, among others, the column redundancy unit and the memory area. The decision made by the column redundancy unit then needs to be transferred back over the data bus, before the read or write operation can take place. Thus, the time it takes to transfer this data over the data bus affects the speed of the memory device.
In general, there exists a need for faster memory devices with increased storage capacity. As a result, the processing of column redundancy data becomes more important and increasingly limits the overall performance of memory devices. Consequently, there is a need for non-volatile semiconductor memory device with increased performance.